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8 Mbit (x16) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle
Bit methods. See Figures 12 and 13 for timing waveforms and Figure 26 for the flowchart. Any com-
mands issued during the Sector- or Block-Erase operation are ignored. When WP# is low, any attempt
to Sector- (Block-) Erase the protected block will be ignored. During the command sequence, WP#
should be statically held high or low.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing
data to be read from any memory location, or program data into any sector/block that is not suspended
for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-
Suspend command (B0H). The device automatically enters read mode typically within 20 μs after the
Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address location within erase-suspended sectors/
blocks will output DQ 2 toggling and DQ 6 at ‘1’. While in Erase-Suspend mode, a Word-Program opera-
tion is allowed except for the sector or block selected for Erase-Suspend.
To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue
Erase Resume command. The operation is executed by issuing one byte command sequence with
Erase Resume command (30H) at any address in the last Byte sequence.
Chip-Erase Operation
The SST39VF801C/802C and SST39LF801C/802C provide a Chip-Erase operation, which allows the
user to erase the entire memory array to the ‘1’ state. This is useful when the entire device must be
quickly erased.
The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase
command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising
edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is
Toggle Bit or Data# Polling. See Table 7 for the command sequence, Figure 11 for timing diagram, and
Figure 26 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When
WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence, WP# should
be statically held high or low.
Write Operation Status Detection
The SST39VF801C/802C and SST39LF801C/802C provide two software means to detect the comple-
tion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software
detection includes two status bits: Data# Polling (DQ 7 ) and Toggle Bit (DQ 6 ). The End-of-Write detec-
tion mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase opera-
tion.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a
Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this
occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with
either DQ 7 or DQ 6 . In order to prevent spurious rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed location an additional two (2) times. If both reads
are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
?2011 Silicon Storage Technology, Inc.
8
DS25041A
05/11
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